1. Field
The present invention relates to a non-volatile memory device and, more particularly, to a semiconductor memory device including a multi-page copyback system and method.
2. Related Art
Semiconductor memory devices are generally classified into random access memories (RAMs) and read-only memories (ROMs). RAMs are volatile memories that lose stored data when their power supplies are interrupted. RAMs include dynamic RAMs (DRAMs) and static RAMs (SRAMs). ROMs, on the other hand, are non-volatile memories that maintain stored data even when their power supplies are interrupted. ROMs include programmable ROMs (PROMs), erasable PROMs (EPROMs), electrically EPROMs (EEPROMs), and flash memories. Flash memories are widely used in computers, memory cards, and the like due in part to the capability of erasing data in block form.
Flash memory devices are typically categorized as NOR-type and NAND-type based on the way that memory cells are connected. A NOR-type flash memory device includes at least two cell transistors connected in parallel to a bitline. The NOR-type flash memory device stores data using channel hot electron injection and erases data using the Fowler-Nordheim (F-N) tunneling effect. A NAND-type flash memory device, on the other hand, includes at least two cell transistors connected in cascade to a bitline. The NAND-type flash memory device stores and erases data using the F-N tunneling effect. NOR-type flash memories operate at high speed but are not typically implemented in high integration designs due to high power consumption. NAND-type flash memories, on the other hand, are advantageous in high integration designs due to lower cell current consumption than NOR-type flash memories. Methods of programming and erasing NAND-flash memories are disclosed, e.g., in U.S. Pat. No. 5,473,563 entitled NONVOLATILE SEMICONDUCTOR MEMORY and U.S. Pat. No. 5,696,717 entitled NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY, respectively. We incorporate the '563 and '717 patents by reference.
NAND-flash memory devices support a page copyback operation. The page copyback operation involves copying a source page of data to a target page. For example, if a bad block is generated while data is written into a flash memory device, the bad block is marked as unusable. Previously successfully stored data are read out of the bad block and stored in another block. To do so, a page copyback operation is often used because it reduces the data transfer time significantly.
An exemplary NAND-type flash memory device performing a page copyback operation is disclosed in, e.g., U.S. Pat. No. 6,671,204 entitled NONVOLATILE MEMORY DEVICES WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHOD OF USING THE SAME, which we incorporate by reference. According to the '204 patent, a NAND-type flash memory device needs a complex page buffer having a dual register structure to perform a page copyback operation. Control and configuration of such a dual register structure, however, becomes unwieldy when a plurality of page data must be copied.
Accordingly, a need remains for an improved semiconductor memory device and an associated multi-page copyback method.